Fusing the advantages of optics with electronics promises a number of advantages in VLSI systems. While there are fundamental advantages to using opto-electronic systems, industry acceptance of such systems depends on their cost-benefits relative to fully electrical systems. If the cost of optoelectronic systems is high, their usage will be restricted to niche applications.
Industry leaders, however, expect to use optical boards for their processors in the future. They expect that the future data rates will make electrical board signaling very costly, since it will require increased trace thickness, using exotic substrates with lower dielectric loss tangents, employing differential signaling techniques or more sophisticated transmitters and receivers. All these potential solutions are costly, and make optical interconnect technology an increasingly attractive alternative.
Optical interconnect technology still poses its own cost problems in short-distance applications. This technology depends largely on components made of gallium-arsenide and germanium, which are more expensive than silicon. These components are then integrated with silicon systems using hybrid integration techniques, such as wire bonding, flip-chip bonding and wafer bonding.
Wire-bonding, the simplest of all the hybrid techniques, involves connecting the photodetector chip and the receiver chip with physical wires after fabrication. Wire-bonding thus involves post-fabrication steps leading to an increase in cost and design time. Wire-bonding adds additional parasitic effects, in the form of bond-wire inductance and pad capacitance, and constrains the design of opto-electronic systems. Since wire-bonding pads need to be allocated space on chip, the number of input/output signals is limited.
Detector and receiver chips 3 can be flip-bonded, as shown in FIG. 1 (Prior Art), to eliminate wiring and therefore eliminate the parasitic effects. This technique is efficient only if the receiver/detector substrate is transparent to the light incident on the detector. Otherwise, it requires costly procedures to thin the substrate and make it transparent to the wavelength of light being used. This technique, like wire bonding requires post-fabrication steps. This, along with the precision required in flip bonding, makes the technique costly.
With wafer-bonding, it is possible to bond detector and receiver wafers together. Recent advances in this technology include i) sequential processing, which involves single crystal growth and transfer and ii) parallel processing, which involves fabricating separate wafers and transferring the thinned donor layer. Sequential processing causes degradation of the performance of the lower layers due to thermal cycling. Parallel processing involves issues of reliable thinned wafer transfer. These techniques are still at research stage and are not expected to be low cost. Since these hybrid techniques can be cost-intensive and are not expected to become less expensive, current research is focused on ways to make photodetectors in silicon, eliminating hybrid integration. Constructing opto-electronic systems in silicon can also provide a number of advantages including mature fabrication techniques, ease of design and verification, and, as in the electronics case, improved yields.
With respect to silicon-based photodetectors, in order to improve the bandwidth-efficiency of silicon detectors, either a large on-chip photodiode bias voltage or non-standard processing techniques can be used. Silicon p-n and p-i-n photodiodes can have response time issues due to the long absorption depth at 850 nm. Large bias voltages can improve the carrier velocity, and hence, the response time. However, using an additional power supply voltage can involve additional cost, possibly offsetting any cost benefits that might be incurred from integrating detectors in silicon. Non-standard processing, like using deep trenches, thicker active layer SOI substrates, and fully depleted SIMOX substrates, can restrict the detector applications since they may not be compatible with the logic process fabrication.
A disadvantage of silicon for IR detectors at 850 nm wavelength light has been the long absorption length (¼ 20 μm) required for high responsivity. The thickness of these detectors can degrade bandwidth due to both parasitic effects and carrier transport mechanisms and can make high speed operation with good responsivity a challenge.